Electrical isolation of semiconductor integrated transistors from one another can be achieved by laterally (in the plane of the wafer) isolating "active" regions of the device with insulating material. Two techniques are common: 1) selectively oxidizing wafer silicon surrounding the active region by means of Low Temperature Oxidation (LTO), Local Oxidation of Silicon (LOCOS), or the like, or 2) depositing insulating material, such as silicon dioxide in trenches formed around the active regions.
Regarding the latter technique (trench formation and filling), trenches are typically etched (e.g. plasma etched) into the substrate around the active regions to a depth "d" of from a few hundred Angstroms (.ANG.) to a few microns (.mu.m). A patterned mask, such as silicon dioxide or silicon nitride, is used for etching the trenches, and an etchant such as fluorine and/or chlorine containing gases, are normally used for etching the substrate selectively (preferentially) to the mask material. Commonly, the resulting trenches are overfilled with silicon dioxide ("oxide"), and excess oxide (that which is not within the trench) is removed, such as by polishing--as disclosed in commonly-owned, copending U.S. patent application No. 07/711,624, entitled TRENCH PLANARIZATION TECHNIQUES, and filed on Jun. 06, 1991 by Schoenborn and Pasch.
FIG. 1 shows a semiconductor device 110, including a substrate 112, an etched trench 114 of width "w" and depth "d" adjacent (surrounding) diffusion regions 116, and a mask layer 118 having an opening 120 for allowing etchants 122 to form the trench 114. Ultimately, the trench will be filled with an insulating material, and will form an isolation structure.
The mask 118 can be composed of several layers. In the case of the top layer of the mask 118 being nitride, the bottom layer would be a stress-reducing buffer oxide. The important factor is that layer(s) 118 be designed such that it protects the substrate during trench etch and fulfills subsequent requirements, such as acting as a polish stop layer if a uniform trench-fill insulating material is further planarized by mechanical polishing.
The technique illustrated in FIG. 1 is commonly employed, but does not provide a suitable mechanism for endpoint detection. Therefore, in order to form trenches of equal depth, from wafer-to-wafer (e.g., using a single wafer etcher), or from batch-to-batch (e.g., using a batch reactor), etch rate must be very well controlled, and usually must be measured immediately prior to etching.
Furthermore, in the case of trenches having different sizes (widths), loading effects are uneven and the various size trenches will not etch to the same depth. (Etching to the same depth is generally preferred from the viewpoint of device performance consistency and quality of manufacturing.) For a common range of trench widths, ranging from 10 .mu.m to 1 mm, resulting etch depth can vary widely, which is undesirable as it is a difficult effect to control.
Additionally, while trench depth can be measured with a stylus, such a measuring technique is both slow and destructive.
What is needed is a technique for self-controlling trench etch depth.